1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same.
Priority is claimed on Japanese Patent Application No. 2009-093954, filed Apr. 8, 2009, the content of which is incorporated herein by reference.
2. Description of the Related Art
In order to realize high speed performances, high density packaging and multi-functions of a semiconductor device, and a chip on chip technology has been studied and developed. The chip on chip will be hereinafter, referred to as CoC. In this technology, a plurality of semiconductor chips is stacked over a substrate. The stack of the semiconductor chips is packaged in a single semiconductor package at high density. The CoC technology can also be referred to as a multi-chip package technology, hereinafter, referred to as MCP.
The semiconductor device using the CoC technology, hereinafter, referred to as a CoC semiconductor device, includes a plurality of wired-connected or direct-bonded semiconductor chips. The direct-bond will hereinafter be referred to as flip chip bonding).
The CoC semiconductor device having a plurality of stacked semiconductor chips has an increased thickness. Particularly, it is preferable that a small-sized semiconductor device is integrated in a mobile device such as a mobile phone. In recent years, the requirement for higher density integration or packaging has been on the increase. Increasing the number of stacked semiconductor chips in the semiconductor device increases the total thickness of the semiconductor device, thereby making it difficult to realize the higher density packaging.
If the thickness of individual semiconductor chip is reduced in order to reduce the total thickness of the CoC semiconductor device, this will increase a stress such as a thermal stress due to difference in thermal expansion between sealing resin and the semiconductor chip. The thermal stress is caused by a thermal treatment process. The thermal stress causes a bend of the semiconductor chip so that the side portion of the semiconductor chip slightly rises up and the sectioned shape of the semiconductor chip is concave. Such bend will be called to as “concave-bend”. In particular, the thermal stress is intensively applied to a position which is farthest from the substrate among the stacked semiconductor chips. This position will, hereinafter, be referred to as a top position. The largest concave-bend is generated in the top semiconductor chip which is positioned at the top position of the stack. The concave-bending will cause cracks in the semiconductor chips or the substrate.
Examples of countermeasure technique against these bending problems of the semiconductor chips are disclosed in Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-269861, and JP-A-2007-066932.
Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-269861 and JP-A-2007-066932 each relate to a semiconductor device and a method of forming the same. Each publication discloses a CoC semiconductor device which includes a lower substrate or a wiring board, in which a predetermined wiring is formed. The CoC semiconductor device further includes semiconductor chips which are electrically connected to the lower substrate. The CoC semiconductor device further includes an intermediate member, or a sealing member, which seals the semiconductor chips. The CoC semiconductor device further includes an upper plate which is disposed over the semiconductor chips. The thermal expansion rates of the upper plate and the lower substrate are approximately the same. By using the upper plate and the lower substrate having approximately the same thermal expansion rate, the bending of the semiconductor chip can be reduced.
The semiconductor devices disclosed in Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-269861 and JP-A-2007-066932 are engaged with the following problems. Since the upper plate is arranged in an upper position which is distant from the stacked semiconductor chips, the thickness of the semiconductor device is increased. Since the upper plate is bonded only to the intermediate member, the intermediate member can easily be removed due to mechanical stress or mechanical shock. In addition, since the stacked semiconductor chips are sealed only by molding, voids will be generated between the semiconductor chips, to thereby lower the reliability of the semiconductor device.
Examples of structures which reinforce the CoC semiconductor device are disclosed in Japanese Unexamined Patent Application, First Publications, Nos. JP-A-2006-319243, JP-A-2007-194444, JP-A-2008-294367, and JP-A-2004-165283.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2006-319243 discloses a memory module and a method of forming the same. The memory module includes a memory core chip, an interface chip and an interposer chip. A radiator plate is provided in the vicinity of the interface chip.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2007-194444 discloses a stacked semiconductor device. The stacked semiconductor device includes a first semiconductor chip and a second semiconductor chip, and a connector which connects the first semiconductor chip and the second semiconductor chip.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2008-294367 discloses a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a stacked structure which includes a plurality of semiconductor chips which are arranged on the substrate, and a reinforcement chip. The reinforcement chip is provided on a surface of the stacked structure which is opposite to the substrate or between the substrate and the stacked structure.
Japanese Unexamined Patent Application, First Publication, No. JP-A-2004-165283 discloses a semiconductor device. The semiconductor device includes a first semiconductor chip, a second semiconductor chip which is mounted on a first main surface of the first semiconductor chip, and a wiring board. The first semiconductor chip is mounted on the wiring board so that a second main surface of the first semiconductor chip is directed to the wiring board.
It is difficult for the above-described structures to suppress that the semiconductor chip from is concave-bent by thermal stress in the manufacturing process, and it is difficult to form a thickness-reduced semiconductor device.